1. Field of the Invention
The present invention relates to a method for creating a test clock domain during an integrated circuit design, and more particularly, to a method for creating a test clock domain which can prevent serious local voltage drop within a region.
2. Description of the Prior Art
Devices for circuit detecting and testing are usually required when designing and producing a digital logic circuit. Circuit testing devices in the art include a plurality of flip flop scan cells stitched together to form a scan chain, where predetermined logic values are sequentially loaded into the scan chain to test the digital logic circuit.
During the scan test, if there are too many flip-flops belonging to a same test clock in a specific region of the digital logic circuit—in other words, the density of the flip-flops belonging to the same test clock is too high—more power is required when the flip-flops within the specific region are triggered by a clock signal. A serious transient supply voltage drop will occur to change the behaviors of the elements within the specific region, and the scan chain will thereby fail to detect the digital logic circuit.